1. Field
The following description relates to a method of manufacturing a through-via, which passes through a silicon wafer to electrically connect circuits formed on an upper surface and a lower surface of the silicon wafer to each other.
2. Description of the Related Art
A through-via of a silicon wafer has been developed to achieve a 3-D stacking technology capable of increasing a packing density of electronic components by arranging a processor and a memory above/below each other on an upper surface and a lower surface of the silicon wafer. Recently, there has been keen competition for developing the 3-D stacking technology in packaging industry. A conventional system using silicon based electronic components has been constituted in 2-D constitution, and such a 2-D configuration system has limitations in increasing a packaging density. In addition, with a trend toward a merger of technologies, an intelligent system is required. Accordingly, many studies on integration degree have been conducted to achieve intelligent system. The degree of integration is increased by arranging the electronic components in a 3-D arrangement instead of a 2-D arrangement. In addition, a chip stacking technology through a wire bonding may be also used to increase the degree of integration in a system. Recently, the performance of a processor has been improved, and a memory, a graphic card and peripheral devices have a limitation in keeping up with input/output signal speed of the processor, resulting in a bottleneck phenomenon. In order to improve the input/output signal speed, a through-via is formed in the silicon wafer such that electronic chips are vertically stacked up against each other, thereby shortening a transmission line on layers and increasing the stacking density of input/output terminals. That is, the through-via allows the input/output speed of signals to be remarkably improved. In addition, a technology of reducing a thickness of a silicon wafer into 50 μm or below has been to developed to shorten the transmission line on layers such that transmission speed of signals is further improved.
Meanwhile, silicon carriers requiring a superior mechanical stability and optical components susceptible to external mechanical force include a silicon wafer provided in a great thickness of several hundred micrometers or above. In particular, a stress generated when the silicon wafer is deformed may cause optical characteristics of optical components to be changed, in which the optical components include an optical switch, an arrayed-waveguide grating (AWG) and an optical splitter based on a planer lightwave circuit (PLC). As a result, the insertion loss is increased or the index of refraction is changed so that the optical path is changed. In this regard, the silicon wafer needs to have a substantial thickness greater than several hundred micrometers. For this reason, a through-via needs to have a great depth, and needs to be insulated. In addition, a silicon wafer, which has a maximum electric resistance of about 104 Ωcm, causes a loss of signal power when transmitting input/output signals, and thus is not suitable for high speed transmission.